Improving energy efficiency using a link adaptation algorithm dedicated for 100 Gbps wireless communication |
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| Affiliation: | 1. IHP, Frankfurt (Oder), Germany;2. Brandenburg University of Technology, Cottbus, Germany;1. Department of Communication Engineering of Jilin University, Changchun, Jilin 130025, China;2. Department of Mathematics of Jilin University, Changchun, Jilin 130022, China;1. Dept. of Electrical and Electronics Engineering, Erzincan University, Erzincan, Turkey;2. Dept. of Naval Architecture and Marine Engineering, Bandirma Onyedi Eylul University, Balikesir 10200, Turkey;3. Dept. of Electrical and Electronics Engineering, Istanbul University, Istanbul, Turkey;1. Department of Radio Electronics, Faculty of Electrical Engineering and Communication, Brno University of Technology, Technicka 3082/12, 61600 Brno, Czech Republic;2. Department of Telecommunications, Faculty of Electrical Engineering and Communication, Brno University of Technology, Technicka 3082/12, 61600 Brno, Czech Republic;1. Department of Electrical Engineering, Isfahan (Khorasgan) Branch, Islamic Azad University, Isfahan, Iran;2. Department of Electrical Engineering, Urmia University, Urmia, Iran;3. Department of Electrical Engineering, Military College of Signals (MCS), National University of Science and Technology, Islamabad, Pakistan;4. Young Researchers and Elite Club, Babol Branch, Islamic Azad University, Babol, Iran |
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| Abstract: | This paper presents a link adaptation algorithm dedicated for 100 Gbps wireless transmission. Interleaved Reed-Solomon codes are selected as forward error correction (FEC) algorithms. The redundancy of the codes is selected according to the channel bit error rate (BER). The uncomplicated FEC scheme allows implementing a complete data link layer processor in an FPGA (field programmable gate array). In our case, we use the Virtex7 FPGA to validate the functionality of our implementation. The proposed FPGA-processor achieves 169 Gbps throughput. Moreover, the implementation is synthesized into 40 nm CMOS technology and the described link adaptation algorithm allows reducing consumed energy per bit to values below 1 pJ/bit at BER <1e?4. With higher BER, the energy increases up to ～13 pJ/bit. |
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| Keywords: | Link adaptation Energy consumption Data link layer processing Interleaved Reed-Solomon FPGA |
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