A read disturbance free differential read SRAM cell for low power and reliable cache in embedded processor |
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| Affiliation: | 1. Department of Applied Electronics & Instrumentation, Silicon Institute of Technology, Bhubaneswar, India;2. Department of Electronics and Communication Engineering, N.I.T. Rourkela, India;1. Applied Mathematics and Mathematical Modeling Department, North-Caucasian Federal University, Stavropol, Russia;2. Informational Systems Department, Stavropol State Agrarian University, Stavropol, Russia;3. Informational Systems, Technologies and Communication Department, Service and Technologies Institute, Pyatigorsk, Russia;4. Faculty of Electrification in Agriculture, Stavropol State Agrarian University, Stavropol, Russia;1. MulticoreWare, Inc., St. Louis, MO, USA;2. Department of Electrical and Computer Engineering, Southern Illinois University, Carbondale, IL 62901, USA;1. Department of Electrical and Computer Engineering, University of Sharjah, P.O. 27272, United Arab Emirates;2. Department of Electrical and Computer Engineering, University of Calgary, Alberta, Canada;3. University of Patras, Physics Department, Electronics Laboratory, GR-26504 Rio Patras, Greece;1. The 14th Research Institute of China Electronics Technology Group Corporation, Nanjing 210039, PR China;2. School of Electronic Engineering and Computer Science, Queen Mary University of London, London E1 4NS, UK;3. School of Physics and Electronic Engineering, Shanxi University, Taiyuan 030006, PR China;4. School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa K1N 6N5, Canada;1. 115 Department of Mathematics, Shahrekord University, Iran;2. 19395-5746 School of Mathematics, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran;1. University of Patras, Physics Department, Electronics Laboratory, GR-26504, Rio Patras, Greece;2. Department of Electrical and Computer Engineering, University of Sharjah, Sharjah, PO Box 27272, United Arab Emirates;3. Department of Computer, Electrical and Mathematical Sciences & Engineering, King Abdullah University of Science and Technology (KAUST), 23955 Thuwal, Saudi Arabia |
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| Abstract: | Energy consumption and data stability are vital requirement of cache in embedded processor. SRAM is a natural choice for cache memory owing to their speed and energy efficiency. Noise insertion to the SRAM cell during read is a serious problem which reduces its stability. A read disturbance free differential SRAM cell consisting of seven transistors is proposed here which increases cell stability along with maintaining the most desirable differential read technique for faster read. The read SNM of the proposed cell is 154%, 31% and 58% large than that of the conventional 6T-SRAM cell and 2 other 7T-SRAM cells [5,6] compared here. Various factors such as short circuit current reduction, use of single write access transistor, partial bit line swing etc. reduces the overall energy consumption of the proposed cell by 41% compared to 6T-SRAM cell. The proposed cell is also compared with an eight transistor based read disturbance free SRAM cell. The cell delay of the proposed cell is around 55% lesser than that of the 8T-SRAM cell. Besides CMOS the performance achievement of the proposed 7T-SRAM cell is also validated at miniaturized dimension of 20 nm using FinFET based predictive technology model library. |
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| Keywords: | SRAM Short circuit current Stability Differential read Process variation |
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