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采用异步实现的快速傅里叶变换处理器
引用本文:赵冰,仇玉林,吕铁良,黑勇.采用异步实现的快速傅里叶变换处理器[J].微电子学,2006,36(4):396-399.
作者姓名:赵冰  仇玉林  吕铁良  黑勇
作者单位:中国科学院,微电子研究所,北京,100029
基金项目:国家自然科学基金资助项目(90307004)
摘    要:介绍一种采用异步实现结构的快速傅里叶变换处理器,该处理器的控制采用本地握手信号取代传统的系统时钟。给出了处理器中异步加法器的电路结构,设计了一个采用Booth译码Wallace tree结构的异步乘法器。通过对一个8点的异步快速傅里叶变换处理器进行电路仿真,得到该处理器完成一次变换的平均响应时间为31.15 ns,仅为最差响应时间42.85 ns的72.7%。可见,采用异步方式的快速傅里叶变换处理器在性能方面较同步处理器存在优势。

关 键 词:异步集成电路  异步数据通路  异步乘法器  快速傅里叶变换
文章编号:1004-3365(2006)04-0396-04
收稿时间:2005-10-28
修稿时间:2005-10-282006-01-05

An Asynchronous Implementation of Fast Fourier Transform Processor
ZHAO Bing,QIU Yu-lin,L Tie-liang,HEI Yong.An Asynchronous Implementation of Fast Fourier Transform Processor[J].Microelectronics,2006,36(4):396-399.
Authors:ZHAO Bing  QIU Yu-lin  L Tie-liang  HEI Yong
Affiliation:Institute of Microelectronics , The Chinese Academy of Sciences, Beijing 100029 P. R. China
Abstract:A novel asynchronous implementation of fast Fourier transform(FFT) processor is described.The(asynchronous) FFT processor controls the sequence of logic circuits by local handshake signals,instead of the globe clock.Circuits of asynchronous adder are proposed.An asynchronous multiplier using booth decode and based on Wallace tree architecture is designed.Results of the performance analysis of an 8-point asynchronous FFT processor show that the average case response time,which is 31.15 ns,is only 72.7% of the worst-case response time,which is 42.85 ns,for completing a transform.It reveals that the asynchronous FFT processor has some performance advantages than the synchronous one.
Keywords:Asynchronous IC  Asynchronous data-path  Asynchronous multiplier  Fast Fourier transform
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