| 降低B3G系统中MIMO接收机复杂度的方法 |
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| 引用本文： | 王强,陶小峰,许灵军,舒晶,张平.降低B3G系统中MIMO接收机复杂度的方法[J].北京工业大学学报,2008,34(10). |
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| 作者姓名： | 王强 陶小峰 许灵军 舒晶 张平 |
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| 作者单位： | 北京邮电大学,无线新技术研究所,北京,100876;北京邮电大学,无线新技术研究所,北京,100876;北京邮电大学,无线新技术研究所,北京,100876;北京邮电大学,无线新技术研究所,北京,100876;北京邮电大学,无线新技术研究所,北京,100876 |
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| 基金项目： | 国家自然科学基金重大项目(60496312);;国家“八六三”计划资助项目(2006AA01Z260)． |
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| 摘 要： | 为降低MIMO(多入多出)接收机的FPGA(现场可编程门阵列)实现对资源的消耗,对V-BLAST(垂直-贝尔实验室分层空时码)译码算法进行了简化。使用位宽缩减技术减少算法实现所占用的资源。同时利用符号保护截止技术保障定点运算的性能.仿真显示其性能接近于Golden译码算法,同时复杂度相比Golden译码算法大大降低.对实现方法在Xilinx公司的VirtexII Pro系列FPGA中的资源使用情况进行了统计,并在B3G TDD (时分双工)实验验证平台上进行了验证.结果表明:该实现方法可用于B3G TDD系统的MIMO接收机的硬件实现.
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| 关 键 词： | 接收机 正交频分复用 现场可编程门阵列 |
Method to Reduce the Complexity of MIMO Receiver in B3G System |
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| WANG Qiang,TAO Xiao-feng,XU Ling-jun,SHU Jing,ZHANG Ping.Method to Reduce the Complexity of MIMO Receiver in B3G System[J].Journal of Beijing Polytechnic University,2008,34(10). |
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| Authors: | WANG Qiang TAO Xiao-feng XU Ling-jun SHU Jing ZHANG Ping |
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| Affiliation: | Wireless Technology Innovation Institute;Beijing University of Posts and Telecommunications;Beijing 100876;China |
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| Abstract: | To reduce the resources of MIMO receiver during FPGA implement,this paper simplifies the V- BLAST (Vertical Bell lab Layered Spaced-Time) detection algorithm,applies bit-width reduction technique to save resources,and uses fixed point logic to keep the performance.Simulation shows that the BER (Bit Error Rate) performance is close to Golden detection algorithm,but the complexity is greatly less.Statistics on resource occupation of such schemes in VertexⅡ-Pro Series FPGA of Xilinx Company was given,while the schemes were verified on B3G TDD system hardware platform.The result shows that the simplified implementation schemes are applicable to hardware implementation of B3G TDD system MIMO receiver. |
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| Keywords: | receiver orthogonal frequency-division field programmable gate arrays |
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