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A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7μm CMOS ASIC |
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| Authors: | Donnelly K.S. Yiu-Fai Chan Ho J.T.C. Chanh V. Tran Patel S. Benedict Lau Jun Kim Pak Shing Chau Huang C. Wei J. Leung Yu Tarver R. Kulkami R. Stark D. Johnson M.G. |
| Affiliation: | Rambus Inc., Mountain View, CA; |
| Abstract: | A byte-wide I/O cell with 660 MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear amplifier input receivers. The CAD techniques developed allow the design to be ported to CMOS processes ranging from 0.7 μm to 0.3 μm. The chip is 0.9×3.4 mm2 using 0.3 μm rules |
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