一种基于时间交织流水线架构的高速ADC设计

伴随着宽带雷达系统的发展,信号带宽越来越大,从而对模数转换器(ADC)的转换速度要求也越来越高。为满足宽带系统需求,需要ADC能够在数百兆甚至上GHz转换速度下实现较高精度的数据转换,这对ADC芯片设计提出了很高的要求。基于0.18 μm BiCMOS 工艺,设计了一种时间交织流水线架构的超高速ADC,前端采用一个超高速高精度跟踪保持器,转换核心采用四路并行流水线时域交织工作,内部集成多相位时钟控制电路。实测结果表明:该ADC芯片在800 MS/s 速度下性能良好,部分通道最高工作速度可达1.2 GS/s。

A High Speed Analog-to-digital Converter Design Based on Time-interleaved Pipelined Architecture

The signal bandwith becomes larger and larger with the development of the wide-band rader system. Therefore, the speed of the analog-to-digital converter(ADC) becomes more and more important. To satisfy the wide-band system, the ADC should sample at the speed of hundreds MHz to GHz which is a great challenge for ADC design. This paper gives a design of a high speed ADC based on time-interleaved pipelined architecture in 0.18 um BiCMOS progress. A front-end high speed and high resolution track-and-hold is used for the input sampling. The converter core is consisted of four parrelled pipelined ADC lanes which work at time-interleaved mode. The multi-phase clock generator is integrated in chip. The test results show that the ADC could achieve well performance at 800 MS/s, and some channels can even work at 1.2 GS/s.