Iterative signal reconstruction of deliberately clipped SMT signals

With the aggressive scaling of device technology, the leakage power has become the main part of power consumption, which seriously reduces the energy recovery efficiency of adiabatic logic. In this paper, a novel low-power adiabatic logic based on FinFET devices has been proposed. Due to the lower leakage current, higher on-state current and design flexibility of FinFETs, the proposed adiabatic logic shows considerable power reduction, performance improvement and area saving compared with CMOS adiabatic logic. An 8-state clock chain as the test circuit has been demonstrated based on the 32-nm FinFET Predictive Technology Model. The simulation results show that adiabatic circuit based on FinFET devices achieves a power reduction of up to 84.8% and a limiting frequency of up to 55 GHz.