A 16-ns 1-Mb CMOS EPROM |
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| Authors: | Kuriyama M Atsumi S Imamiya K-I Iyama Y Matsukawa N Araki H Narita K Masuda K Tanaka S |
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| Affiliation: | Toshiba Corp., Kawasaki; |
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| Abstract: | A 16-ns 1-Mb CMOS EPROM has been developed utilizing high-speed circuit technology and a double-metal process. In order to achieve the fast access time, a differential sensing scheme with address transition detection (ATD) is used. A double-word-line structure is used to reduce word-line delay. High noise immunity is obtained by a bit-line bias circuit and data-latch circuit. Sufficient threshold voltage shift (indispensable for fast access time) is guaranteed by a threshold monitoring program (TMP) scheme. The array is organized as 64 K×16 b, which is suitable for 32-b high-performance microprocessors. The active power is 425 mW, the programming time is 100 μs, and the chip size is 4.94×15.64 mm2 |
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