基于EAPR的FPGA局部动态重构实现

针对数字逻辑系统规模扩大出现的单片电路资源利用率下降的问题,提出了一种基于EAPR的FPGA局部动态重构实现方法.该方法结合EAPR设计思想和Virtex-5芯片的特点,通过ISE软件进行模块设计和PlanAhead软件的重构实现,完成了XC5VLX50T（1FF1136）芯片的局部动态重构.仿真和实验结果表明：该方法需下载的文件大小仅为普通方法的21.9%;能实现对芯片内部资源的有效管理和合理利用,为实际工程中利用有限的资源实现更大规模的逻辑设计提供参考.

Realization of FPGA Dynamic Partial Reconfiguration With EAPR

Aimed at the problem of single-chip circuit resource utilization rate being decreasing with the scale of digital logic system expanding,an approach to implementing FPGA dynamic partial reconfiguration was proposed based on EAPR.Combined with the design idea of the EAPR and the characteristics of Virtex-5 chips,the dynamic partial reconfiguration of XC5VLX50T（1FF1136） chip was realized by using ISE software to carry out the module design and the implementation of PlanAhead software reconfiguration.The simulation and experiment results show that the required size of files downloaded in this approach is only 21.9% of that in conventional method,implementing the effective management and reasonable utilization of the internal resource of chip,which provide a theoretical reference for utilizing limited resources to realize larger scale of logic design in engineering.