| 基于Verilog HDL的流水线模型机的设计与实现 |
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| 引用本文： | 易小琳,彭一凡.基于Verilog HDL的流水线模型机的设计与实现[J].北京工业大学学报,2007,33(10):1096-1101. |
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| 作者姓名： | 易小琳 彭一凡 |
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| 作者单位： | 北京工业大学,计算机学院,北京,100022;北京工业大学,计算机学院,北京,100022 |
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| 摘 要： | 为了提高模型机指令执行的并行性,使用Verilog HDL并采取top-down设计方法,利用确定的有限状态自动机(DFA)理论,设计并实现了一台具有指令级并行性的流水线模型机的方案.阐述了该流水线模型机的DFA设计算法与Verilog HDL的实现方法,并给出了相应的仿真测试.测试结果证明,该模型机能并行处理4条指令,并具有预取指令和旁路功能.
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| 关 键 词： | 流水线 Verilog HDL描述 微处理器 确定的有限状态自动机 |
| 文章编号： | 0254-0037（2007）10-1096-06 |
| 修稿时间： | 2006-09-07 |
Design and Implementation of a Pipeline Model Machine Based on Verilog HDL |
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| YI Xiao-lin,PENG Yi-fan.Design and Implementation of a Pipeline Model Machine Based on Verilog HDL[J].Journal of Beijing Polytechnic University,2007,33(10):1096-1101. |
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| Authors: | YI Xiao-lin PENG Yi-fan |
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| Affiliation: | College of Computer Science, Beijing University of Technology, Beijing 100022, China |
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| Abstract: | In order to raise parallelism of executing instructions by model machine,this paper introduces the schema of designing a pipeline model machine.Using Verilog HDL,a pipeline model machine with parallelism of instructions which is combined with top-down method and DFA is implemented.This paper describes the schema and some algorithms of the pipeline model machine and simulates this machine in the end.The simula- tion results show that the model machine can process 4 instructions at the same time,and has the per-for- mances of pre-fetching instructions and bypassing. |
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