SOC芯片的高速模拟IP测试方法学

很多SoC芯片里会使用SATA物理层,PCIE物理层以及DDR2/DDR3物理层等高速模拟IP。这些高速模拟IP需要被自动测试设备完整的测试。自动测试设备的高速测试选项就是用来测试高速IP,但随之而来的是测试成本的增加。智原科技利用内建自测试方法来取代费钱的自动测试设备的高速测试选项。内建自测试提供了最具成本效率的方法。高速模拟IP内建自测试的故障覆盖率很高,所以我们不再需要自动测试设备的高速测试选项及其所带来的高成本。

Test Methodology for High Speed IP in SoC Chip

SATA PHY, PCIE PHY, and DDR2/DDR3 PHY IPs are used in many SOC ICs. Those high speed analog IPs need to be fully tested by Automatic-Testing-Equipment （ ATE ）. The ATE high speed testing options could be used for high speed IP testing, but the testing cost would be increased. Faraday uses Built-In-Self-Test （ BIST ） instead of ATE high speed testing options to test the high speed IPs. BIST provides the most cost efficient solution. The fault coverage of high speed IP BIST is very good, ATE high speed testing options are not required anymore, and testing cost will not be increased.