基于FPGA的回波模拟器设计与实现

回波模拟器主要完成对雷达引信机射频信号的延迟和衰减,并传输至接收端.传统的模拟延时和模拟衰减通常采用多路开关控制延迟线的方法实现,由于模拟电路存在温度漂移、器件老化影响、抗干扰性能差等缺点,从而使得输入信号质量下降,线路越长,噪声的积累也就越多.以现场可编程门阵列Vertex-5系列的FPGA为核心,研究了数字化回波模拟器总体设计方案,综合利用了模数转换、数字下变频DDC、数字延迟衰减等技术,实现了雷达引信机射频信号的延迟衰减精确可调,完成了频率、功率信号的实时测量,简化了回波模拟器硬件结构,提高了系统集成度和可靠性.

Design and implement of digital echo simulator based on FPGA

Echo simulator mainly completed to the delay and attenuation of radar fuze machine RF signal,and transmitted to the receiving end. Traditional analog delay and analog attenuation commonly used multi-channel switch delay line to achieve the existence of temperature drift, the device aging effects, anti-jamming performance and poor shortcomings, which makes the decline in the quality of the input signal, the longer the line, the noise due to analog circuit the accumulation of more. Overall design of digital echo simulator was researched, which made series field programmable gate array of Vertex-5 FPGA to be the core of components. Comprehensive utilization of A/D convert, DDC, digital delay and attenuation technologies were used and made the delay or attenuation of altimeter emission signal feasible to be controlled accurately. The technologies accomplished the measurement of real-time frequency and power, simplified the structure of components, improved integration and stability of the system.