A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter |
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| Authors: | Roovers R Steyaert MSJ |
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| Affiliation: | ESAT, Katholieke Univ., Leuven, Heverlee; |
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| Abstract: | A 175 Ms/s A/D converter with a latency of one clock cycle is designed in a 0.7 μm digital CMOS technology. The resolution of the converter is 6 b while the power dissipation is only 160 mW. The A/D converter architecture is based on a continuous time analog preprocessing topology. A continuous time current interpolation circuit is implemented. The performance of the A/D converter is ruled by a tradeoff between speed, power, and accuracy |
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