| CMOS电路ESD保护结构设计 |
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| 引用本文： | 张伟,唐拓.CMOS电路ESD保护结构设计[J].微处理机,2010,31(2):30-31,35. |
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| 作者姓名： | 张伟 唐拓 |
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| 作者单位： | 中国电子科技集团公司第四十七研究所,沈阳,110032 |
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| 摘 要： | 静电放电是CMOS电路中最为严重的失效机理之一,严重的会造成电路自我烧毁.论述了CMOS集成电路ESD保护的必要性,研究了在CMOS电路中ESD保护结构的设计原理,分析了该结构对版图的相关要求,重点讨论了在I/O电路中ESD保护结构的设计要求.
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| 关 键 词： | 静电放电 可控硅 闩锁 |
CMOS Circuit the ESD Protect the Construction Design |
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| ZHANG Wei,TANG Tuo.CMOS Circuit the ESD Protect the Construction Design[J].Microprocessors,2010,31(2):30-31,35. |
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| Authors: | ZHANG Wei TANG Tuo |
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| Affiliation: | ZHANG Wei,TANG Tuo(The 47th Research Institute of China Electronics Technology Group Corporation,Shenyang 110032,China) |
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| Abstract: | ESD effect is one of the most important invalidation mechanisms,which causes circuit invalid,and even self-burnt.The necessity of ESD protection for CMOS IC is discussed.The article studied the principle of ESD protection structure in the CMOS circuit,analyzed the related requests that the structure needs towards layout,and also placed an emphasis on discussion about the design rules of ESD protection structure in the I/O circuit. |
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| Keywords: | ESD SCR Latch-up |
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