Verilog Testbench设计技巧和策略

仿真Testbench的设计是Top-Down流程中非常关键的一个环节,但是很多设计者却感到困难较大。实际上,verilogHDL有着较强的行为建模能力,可以方便地写出更加高效、简洁的行为模型。论文结合一个ATM测试平台的Testbench设计,讨论了Testbench的结构和总线功能模型(BFM),并对使用BFM模型进行Testbench设计的策略和方法进行了探讨,希望能对广大设计者有所帮助。

Strategy and Technique of Testbench Design in Verilog

Writing testbench is a very critical step in the Top-Down design flow,however,many designers feel difficult to do it well.In fact,designers can write more efficient and concise behavioral modeling testbench using verilog HDL.In this paper,through a testbench design of ATM testing platform,the authors discuss the structure of testbench and the bus function model(BFM).They also discuss the strategy and method of designing testbench with BFM.The authors hope more readers and designers can benefit from it.