一种分组并行的范式霍夫曼编码VLSI结构

设计了一种基于状态机的分组并行加速排序的范式霍夫曼编码VLSI结构。取代了传统的串行排序方法,以分组并行排序的方式来加速频数和码长的计算过程,最终通过减少计算的时钟周期数来达到加速编码的目的。基于SMIC 0.18μm标准工艺,使用Synopsys Design Compiler对该结构进行逻辑综合。实验结果表明,相比于文献[1]的排序结构,编码256个字符时,该结构的编码速度提升约165%;压缩不同质量的100张图片时,最坏情况下平均压缩率提升了2.78%,最好情况下平均压缩率提升了12.24%。

A Canonical Hoffman Coding VLSI Architecture with Grouping Parallel

A grouped parallel accelerated sorting VLSI architecture of Canonical Huffman coding based on the state machine was introduced. Instead of applying the traditional serial sorting method, the parallel grouping sorting method was used to speed up the calculation of frequency and code length. Finally, the purpose of accelerating the coding was achieved by reducing the number of clock cycles. The architecture was synthesized by Synopsys Design Compiler, based on SMIC 0.18 μm standard cell library. The experimental results showed that the encoding speed increased by 165% compared to the architecture proposed in Ref. [1] when encoding 256 characters, and the average compression rate was increased to 2.78% in the worst case and 12.24% in the best case while 100 images of different quality were compressed.