基于FPGA的TDI—CCD时序电路设计

介绍TDI—CCD的特点、工作原理，根据项目所使用的TDI—CCD的使用要求，设计一种基于Ahera公司的现场可编程门阵列（FPGA）EP3C25Q240的TDI—CCD驱动时序电路，驱动时序使用VHDI。语言编写，在Quartus1I平台上进行时序仿真，通过在硬件电路中的测试结果表明，驱动时序满足该款产品的要求。该实验的主要目的是验证这款TDI—CCD的性能，为其应用和进一步的性能改善获得必要的数据，以促进国产CCD的发展及应用。

Design of TDI-CCD Driving Circuit Based on FPGA

The TDI- CCD product＇s characteristics and its working principle,on the basis of TDI- CCD product＇s charac- teristics and the using demand are introduced,the driving schedule is realized on Altera Company＇s Field Programmable Gate Array （FPGA） EP3C25Q240,the driving schedule is written by VHDL language and it has been successfully carried through the timing simulation with Quartus Ⅱ software, results of the hardware electrocircuit test prove that the timing simulation meets the product＇s demand. The main purpose of this experiment is to validate this product＇s performance. It is used to obtain the necessary data to promote development and application of the domestic CCD.