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支持双拓扑结构的片上网络评估高层仿真平台
引用本文:胡婧瑾,潘 赟,严晓浪,MOTTEN Andy,CLAESEN Luc.支持双拓扑结构的片上网络评估高层仿真平台[J].计算机应用研究,2013,30(9):2827-2830.
作者姓名:胡婧瑾  潘 赟  严晓浪  MOTTEN Andy  CLAESEN Luc
作者单位:1. 浙江大学 超大规模集成电路设计研究所,杭州,310027
2. 哈撒尔特大学 信息技术EDM, 比利时 哈撒尔特 3590
基金项目:国家自然科学基金资助项目(61204030); 浙江省自然科学基金资助项目(LQ12F04002)
摘    要:为实现高效的NoC(片上网络)性能评估, 缩短系统芯片的开发周期, 针对时钟精确级的NoC仿真方法进行研究, 提出了一种新型的高层次、高效率仿真平台, 与仅支持网格拓扑结构的传统仿真器相比, 其创新地支持了网格和环型双拓扑结构的性能评估, 同时支持虚通道扩展的路由器结构设计, 能快速得到网络的延迟、吞吐率、功耗等性能结果。实验结果表明, 该仿真平台能准确模拟NoC功能行为, 快速获得其仿真性能, 为NoC设计验证提供了高效的方法。

关 键 词:片上网络  性能评估  高层仿真  环型拓扑  网格拓扑

Two-topology based high-level simulation platform for NoC performance evaluation
HU Jing-jin,PAN Yun,YAN Xiao-lang,MOTTEN Andy,CLAESEN Luc.Two-topology based high-level simulation platform for NoC performance evaluation[J].Application Research of Computers,2013,30(9):2827-2830.
Authors:HU Jing-jin  PAN Yun  YAN Xiao-lang  MOTTEN Andy  CLAESEN Luc
Affiliation:1. Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China; 2. Information Technology-EDM, University Hasselt, Hasselt 3590, Belgium
Abstract:Aiming at realizing efficient performance evaluation of NoC, and reducing SoC (system-on-chip) development period, this paper proposed a new high-level, high-efficiency, cycle-accurate NoC simulation platform. Different from conventional tools, it supported evaluation for both 2D mesh and ring topologies and virtual channel extension in router structure design. It efficiently gave performance results, including average latency, throughput and energy consumption. Experimental results demonstrate that this simulation platform can simulate NoC behavior and obtain performance evaluation results, which provides high-efficiency verification method for NoC design and optimization.
Keywords:network-on-chip(NoC)  performance evaluation  high-level simulation  ring topology  2D mesh
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