Calculating the FHT in hardware |
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Authors: | Erickson AC Fagin BS |
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Affiliation: | Sequoia Systems Inc., Marlboro, MA; |
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Abstract: | A parallel, pipelined architecture for calculating the fast Hartley transform (FHT) is discussed. Hardware implementation of the FHT introduces two challenges: retrograde indexing and data scaling. A novel addressing scheme that permits the fast computation of FHT butterflies is proposed, and a hardware implementation of conditional block floating point scaling that reduces error due to data growth with little extra cost is described. Simulations reveal a processor capable of transforming a 1 K-point sequence in 170 μs using a 15.4 MHz clock |
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