首页 | 本学科首页   官方微博 | 高级检索  
     

用芯片嵌入技术创新移动应用中的2D和3D封装结构
作者姓名:Ron Huemoeller  Corey Reichman  Curtis Zwenger
作者单位:安靠封装测试,美国
基金项目:感谢衷心感谢全球半导体联合会(GSA,Global Semiconductor Alliance)允许我们以中文再次发表本文.
摘    要:智能移动装置的高速发展正在驱动更先进芯片封装技术的开发,以满足多功能集成和小型化的要求。传统的解决方案,如多芯片模块,可能无法同时满足高密度和小型化需求。而先进的2.5D硅基板TSV解决方案成本太高,特别是,在对成本敏感的消费类市场中不能使用。在这两者之间,芯片嵌入式封装可能是一个理想的解决方案,它不但有较高互联密度,较小封装尺寸,也可以实现多芯片集成。本文着重讨论了主动芯片的嵌入技术:二维扇出封装和三维封装叠加。二维结构包括扇出晶圆级封装和多层板中芯片嵌入,前者基于晶圆形式,后者基于型板形式。不同流程的选择造成成本和成品率的差异,也造成芯片放置时间的先后。本文讨论了"Die-First"、"Die-Mid"和"Die-Last"流程的优劣势。主动(有源)芯片嵌入的三维叠加有着与二维芯片嵌入类似的优势,只是主动芯片嵌入封装体的上端可以另外叠加封装体,以实现真正的SiP结构。本文还讨论了芯片嵌入技术的发展、未来增长、可能的封装形式和将来的路线图。

关 键 词:芯片嵌入  多层板芯片嵌入  基于型板组装  TSV  SiP

Embedded Die Packaging Technologies Enable Innovative 2D and 3D Structures for Portable Applications
Ron Huemoeller,Corey Reichman,Curtis Zwenger.Embedded Die Packaging Technologies Enable Innovative 2D and 3D Structures for Portable Applications[J].China Integrated Circuit,2014(6):69-74.
Authors:Ron Huemoeller  Corey Reichman  Curtis Zwenger
Affiliation:Ron Huemoeller, Corey Reichman, Curtis Zwenger (Amkor Technology, Inc.1900 South Price Road, Chandler, AZ 85286, USA)
Abstract:The dramatic growth in "smart" portable electronics is driving the need for a more sophisticated IC packaging approach that allows room for increasing functionality while meeting ever decreasing form factor requirements. Traditional solutions like Multi-Chip Modules ( MCM )may not meet the intense I/O requirements and form factor restrictions concurrently. On the other hand, advanced solutions like 2.5D TSV silicon interposer may prove to be cost prohibitive, especially for applications serving cost-sensitive consumer markets. In the middle, however, embedded die packaging may strike the ideal combination with an increased I/O density, reduced footprint, and multi-die capability within a single IC architectures. Passive device package. Embedded die packaging itself is diverse and can be configured in a variety of embedding is discussed, but the paper focuses primarily on active die embedding. Active die embedding has two general constructions: either as a 2D fan-out package or a 3D stacked package for higher levels of system integration. The 2D formats include platforms such as Fan Out Wafer Level packaging ( FO-WLP ) and embedded die in laminate. One of the primary differences in the 2D structures is the processing format, the former on wafer and the latter on laminate panel. The choice between processing formats can have a significant impact on both cost and yield. The other difference between 2D formats is the timing of the die placement in the process flow. The benefits and disadvantages of "Die First", "Die Last" and "Die Mid" placement are discussed. The other active embedded die format is the 3D stacked package format with a modular System in Package ( SiP ) approach. 3D formats have similar distinctions as 2D formats, only with the added element of stacking one or more packages for a true SiP architecture. This paper also covers the evolution of embedded die, along with its projected growth, packaging formats and future roadmaps
Keywords:Embedded die  Embedded die in laminate  Panel-based assembly  SiP  TSV
本文献已被 CNKI 维普 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号