Threshold voltage model for deep-submicron fully depleted SOI MOSFETs with back gate substrate induced surface potential effects

A simple analytical threshold voltage model for short-channel fully depleted SOI MOSFETs has been derived. The model is based on the analytical solution of the two-dimensional potential distribution in the silicon film (front silicon), which is taken as the sum of the long-channel solution to the Poisson's equation and the short-channel solution to the Laplace equation, and the solution of the Poisson's equation in the silicon substrate (back silicon). The proposed model accounts for the effects of the back gate substrate induced surface potential at the buried oxide-substrate interface which contributed an additional 15–30% reduction in the threshold voltage for the devices used in this work. Conditions on the back gate supply voltage range are determined upon which the surface potential at the buried oxide-substrate interface is accumulated, depleted, or inverted. The short-channel associated drain induced barrier lowering effects are also included in the model. The model predications are in close agreement with PISCES simulation results. The equivalence between the present model and previously reported models is proven. The proposed model is suitable for use in circuit simulation tools such as Spice.