Decomposition methods for scheduling semiconductor testing facilities

We present decomposition procedures for scheduling semiconductor testing facilities. These facilities are characterized by the presence of different types of work centers, some of which have sequence-dependent setup times and some parallel identical machines. We exploit the structure of the routings in semiconductor testing to develop tailored decomposition procedures that decompose the shop into a number of work centers that are scheduled using specialized procedures. Extensive computational experiments show that these procedures significantly outperform existing methods in reasonable CPU times. These results indicate that decomposition methods can be successfully applied to complex scheduling problems of the type addressed in this paper, as well as the classical job shop problems addressed in previous research.