高效能,低功耗DDR2控制器的硬件实现

随着SoC芯片内部总线带宽的需求增加,内存控制器的吞吐性能受到诸多挑战。针对提升带宽性能的问题,可以从两个方面考虑,一个办法是将内存控制器直接跟芯片内部几个主要占用带宽的模块连接,还要能够对多个通道进行智能仲裁,让他们的沟通不必经过内部的AMBA总线,甚至设计者可以利用高效能的AXI总线来加快SoC的模块之间的数据传输。另一个办法就是分析DDR2SDRAM的特性后设计出带有命令调度能力的控制器来减少读写次数,自然就能够降低SoC芯片的功耗,为了节能的考虑还要设计自动省电机制。本文为研究DDR2SDRAM控制器性能的提升提供良好的思路。

Hardware Implementation of a High Performance and Low Power DDR2 Controller

Along with the requirements to the bandwidth of SoC internal system bus, it brings the challenges of the high-throughput to a memory controller. For improving the bus bandwidth, we get two considerations. One is to connect the memory controller directly to the major modules which are bandwidth-hungry, and do smart arbitration to these channels so that they can communicate without having to go through the AMBA bus. Even more, designer can use AXI bus to speed up the data transmission between modules in SoC. The other one is to analyze the features of DDR2 SDRAM and design the memory controller with then it reduce the power consumption of the SoC chip. the command scheduler to reduce the read/write cycles, and We also design the auto power down mechanism to reduce energy consumption. This study provides a good idea to improve performance of DDR2 SDRAM controller.