低压工作的高速10bit Pipelined ADC

本文提出了一种低压工作的高速1Obit Pipelined ADC。采用自举时钟采样和Cascode频率补偿等方法，该ADC可以在低电压下工作，并达到较高的带宽。该ADC在HJTC 0.18-μm CMOS数模混合工艺下进行了设计仿真和流片测试，结果表明：当供电电压为1．8V，采样频率为62．5MSample／s时，所设计的ADC对于1MHz的输入信号转换有效位数可以达到52．2dB SFDR、44．8dB SNR和44．3dB SNDR。

A low voltage high speed 10bit pipelined ADC

A low voltage high speed pipelined ADC is proposed. Through the techniques of bootstrapped switch and cascode frequency compensation, the ADC achieves a SFDR of 52.2 dB, a SNR of 44.8 MHz when working at a 62.5MSample/s clock, a 1MHz input sine signal, and a 1.8 V supply voltage, and the power dissipation is 136mW. It was fabricated in HJTC 0.18-μm CMOS mixed-signal technology.