首页 | 本学科首页   官方微博 | 高级检索  
     

基于IEEE-1588的高精度时钟同步系统设计
引用本文:谭超,苏超,胡诗俊,吴燕,何旭东. 基于IEEE-1588的高精度时钟同步系统设计[J]. 电子器件, 2016, 39(5)
作者姓名:谭超  苏超  胡诗俊  吴燕  何旭东
基金项目:三峡大学2015年硕士学位论文培优基金
摘    要:为提高高速铁路地震预警系统采集设备时间同步精度,本文设计了基于IEEE-1588的网络高精度时钟同步系统。系统利用STM32+FPGA构架搭建硬件平台,在FPGA中利用PLL延迟测量法实现高精度时间间隔测量,时间间隔测量精度达到600ps;利用PHY芯片DP83640获取网络PPS时钟,在STM32中结合卡尔曼滤波与PID算法,实现网络PPS时钟对本地时钟的校正,以及对本地PPS相位校正,最终完成同步系统的软件设计。测试结果表明:本设计时钟同步误差优于3ns,且具备长期稳定性。

关 键 词:IEEE-1588;分布式数据采集;时钟同步;PLL延迟测量法

Design of High Precision Time Synchronization System Based on IEEE-1588
Abstract:In order to improve the precision of data acquisition equipment of the earthquake early warning system for high speed railway, this paper designs a high precision time synchronization system based on IEEE-1588.The system uses STM32+FPGA structure to set up a hardware, achieves high precision time interval measurement based on PLL delay measurement in FPGA, of which measurement accuracy is 600ps. The system obtains network time by PHY chip DP83640, and combines Kalman filtering and PID algorithm in STM32 to correct local time and PPS phase by network time, to complete software design of the synchronization system. The test result shows that: error of time synchronization is less than 3ns and maintain long-term stability.
Keywords:IEEE-1588  distributed data acquisition  time synchronization  PLL delay measurement
点击此处可从《电子器件》浏览原始摘要信息
点击此处可从《电子器件》下载免费的PDF全文
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号