A 1.8-V 91-dB DR second-order ΣΔ modulator in 0.18-μm CMOS technology

This paper deals with the implementation of a second-order ΣΔ modulator in 0.18-μm CMOS technology. The analog-to-digital converter structure combines a 1-bit approach along with a high oversampling ratio (OSR). A silicon circuit prototype, including the modulator itself, a current reference, and the clock signals generator, was designed to operate with a 1.8-V supply, fabricated and tested. Measured values of 87 dB and 91 dB were obtained for the signal-to-noise-plus-distortion ratio (SNDR) and the dynamic range (DR), respectively, for a clock frequency of 8 MHz and an OSR of 256. The effective number of bits (ENOB) was above 14. The experimental performance of the ΣΔ modulator maintains a good level over a modulator clock range higher than 16 MHz, featuring an ENOB equal to 13 at 16 MHz.