面向卷积神经网络的FPGA加速器架构设计

随着人工智能的快速发展,卷积神经网络(CNN)在很多领域发挥着越来越重要的作用。分析研究了现有卷积神经网络模型,设计了一种基于现场可编程门阵列(FPGA)的卷积神经网络加速器。在卷积运算中四个维度方向实现了并行化计算;提出了参数化架构设计,在三种参数条件下,单个时钟周期分别能够完成512、1024、2048次乘累加;设计了片内双缓存结构,减少片外存储访问的同时实现了有效的数据复用;使用流水线实现了完整的神经网络单层运算过程,提升了运算效率。与CPU、GPU以及相关FPGA加速方案进行了对比实验,实验结果表明,所提出的设计的计算速度达到了560.2 GOP/s,为i7-6850K CPU的8.9倍。同时,其计算的性能功耗比达到了NVDIA GTX 1080Ti GPU的3.0倍,与相关研究相比,所设计的加速器在主流CNN网络的计算上实现了较高的性能功耗比,同时不乏通用性。

Design of FPGA Accelerator Architecture for Convolutional Neural Network

With the rapid development of artificial intelligence,convolutional neural networks(CNN)play an increasingly important role in many fields.In this paper,the existing convolutional neural network model is analyzed,and a convolutional neural network accelerator based on field-programmable gate array(FPGA)is designed.In the convolution operation,the parallelization calculation is realized in four dimensions.A parametric architecture design is proposed.Under the three parameters,a single clock cycle can complete 512,1024,2048 multiply and accumulate respectively;the on-chip double buffer is designed.The structure reduces the off-chip storage access and realizes effective data multiplexing.The pipeline is used to implement a complete neural network single-layer operation process,which improves the operation efficiency.Compared with CPU,GPU and related FPGA acceleration schemes,the experimental results show that the speed of the design proposed by this paper is 560.2 GOP/s,which is 8.9 times that of the i7-6850K CPU.At the same time,calculated performance and power consumption ratio is 3.0 times that of NVDIA GTX 1080Ti GPU.Compared with related research,the accelerator designed achieves a high performanceto-power ratio in mainstream CNN network computing,and there is no lack of versatility.