炉管制程工艺中的片数效应及其优化方案

随着半导体技术的发展，越来越多的立式炉管在200mm及300mm集成电路晶圆制造中被应用到。同时炉管制程中的片数效应随着集成电路芯片的集成度越来越高而被凸显出来。文章将以LPCVD氮化硅在0.16μm、64M堆叠式内存制造过程中的片数效应为例，阐述炉管制程工艺中的片数效应以及通过调整制程参数（温度、沉积时间）的方式予以解决的实例。文中通过调整炉管上中下的温度来补偿气体的分布不均匀，调整沉积时间来补偿不同片数的沉积速率的差异，两者结合并辅以基于片数的分片程式来解氮化硅电介质沉积的片数效应。同时以此为基础总结出炉管片数效应的解决方案。

Loading Effect of Furnace Process and the Improvement

More and more vertical furnaces were used in the semiconductor manufacturing of 200mm and 300mm wafers. Loading effect behavior of nitride deposition process was found and investigated in this paper. As opposed to conventional-low pressure chemical vapor deposition (LPCVD), the thickness of pattern run is slightly smaller than that of control run in nitride deposition process. Improved loading effect and wafer-to-wafer uniformity were obtained through the fine tune of process parameters, and the general rules to reduce the loading effect was proposed. The tuning of temperature was used to solve thickness difference that was caused by different gas density. Different deposition time of different wafer quantity was used to cover the difference of deposition rate.