| 基于CPLD的可编程数字频率计的设计 |
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| 引用本文： | 高鹏,张恩平.基于CPLD的可编程数字频率计的设计[J].信息技术与信息化,2002(4):27-30. |
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| 作者姓名： | 高鹏 张恩平 |
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| 作者单位： | 济南大学信息学院,济南,250022 |
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| 摘 要： | 采用美国Lattice公司生产的在系统可编程 (ISP)大规模集成逻辑器件 (CPLD)ispLSI 10 32E芯片实现可编程数字频率计的设计 ,其设计方法简便、高效、无风险 ,且能提高系统的可靠性及灵活性。
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| 关 键 词： | CPLD ISP技术 在系统可编程逻辑器件 数字频率计 |
| 修稿时间： | 2002年8月11日 |
Design of Programmable Frequency Counter Based on ispLSI 1032E Devices |
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| GAO Peng,ZHANG En-ping.Design of Programmable Frequency Counter Based on ispLSI 1032E Devices[J].Information Technology & Informatization,2002(4):27-30. |
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| Authors: | GAO Peng ZHANG En-ping |
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| Affiliation: | GAO Peng ZHANG En-ping |
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| Abstract: | A kind of programmable frequency counter is acted as an example in this paper. This paper provides a design means of programmable digital frequency counter by applying an ispLSI 1032E-70LJ84 device made in American Lattice company. It provides the design with convenience, high-efficiency and none-risk together with the improvement of reliability and flexibility of the system. |
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| Keywords: | Complex programmable logic device In-system programmable technique In-system programmable logic device Digital frequency gauge |
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