| 基于CPLD的可编程数字频率计的设计 |
| |
| 引用本文： | 高鹏,张恩平. 基于CPLD的可编程数字频率计的设计[J]. 信息技术与信息化, 2002, 0(4): 27-30 |
| |
| 作者姓名： | 高鹏 张恩平 |
| |
| 作者单位： | 济南大学信息学院,济南,250022 |
| |
| 摘 要： | 采用美国Lattice公司生产的在系统可编程 (ISP)大规模集成逻辑器件 (CPLD)ispLSI 10 32E芯片实现可编程数字频率计的设计 ,其设计方法简便、高效、无风险 ,且能提高系统的可靠性及灵活性。
|
| 关 键 词： | CPLD ISP技术 在系统可编程逻辑器件 数字频率计 |
| 修稿时间： | 2002-08-11 |
Design of Programmable Frequency Counter Based on ispLSI 1032E Devices |
| |
| GAO Peng ZHANG En-ping. Design of Programmable Frequency Counter Based on ispLSI 1032E Devices[J]. Information Technology & Informatization, 2002, 0(4): 27-30 |
| |
| Authors: | GAO Peng ZHANG En-ping |
| |
| Affiliation: | GAO Peng ZHANG En-ping |
| |
| Abstract: | A kind of programmable frequency counter is acted as an example in this paper. This paper provides a design means of programmable digital frequency counter by applying an ispLSI 1032E-70LJ84 device made in American Lattice company. It provides the design with convenience, high-efficiency and none-risk together with the improvement of reliability and flexibility of the system. |
| |
| Keywords: | Complex programmable logic device In-system programmable technique In-system programmable logic device Digital frequency gauge |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
