PCI总线目标接口状态机的Verilog HDL实现

随着计算机技术的发展，PCI总线以其高性能、突发传输和即插即用的优点获得广泛应用，成为事实上的计算机标准总线。介绍了采用独热（one-hot）编码方式、用Verilog HDL语言实现了PCI目标接口的核心控制部分——目标接口状态机，给出了详细的状态转移图和仿真结果图，并进行了分析。同时结合其它支持模块，灵活地配置到CPLD中实现了PCI目标接口，较好地完成了PCI目标接口的数据传输控制功能。

Implementation of PCI bus object interface status machine using Verilog HDL

With the development of computer technology, PCI bus is widely used because of its strongpoints, such as high-powered, burst transaction, plug and play etc. Using one-hot coding mode and the core controlling part of PCI object state machine using VHDL are introduced. Then the detailed state transferring map and the simulation results figure are given. Combining with other modules, this method can collocate with CPLD to implement PCI object interface, and achieve the data transmission and controlling function of PCI object interface perfectly.