| 一个ECL可预置数四位二进递减计数器的设计 |
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| 引用本文： | 王若虚. 一个ECL可预置数四位二进递减计数器的设计[J]. 微电子学, 1993, 23(2): 15-21,32 |
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| 作者姓名： | 王若虚 |
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| 作者单位： | 机电部第24研究所 四川重庆630060 |
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| 摘 要： | 本文根据用户提出的ECL可预置数四位二进递减计数器技术指标进行正向设计,确定了相应的逻辑功能,设计出了具体的计数器电路。经计算机模拟,所有结果都符合设计要求。电路采用3μm设计规则设计,用氧化物隔离等平面S型双极工艺和全离子注入技术制造。最小发射极尺寸为3μm×10μm,晶体管f_T为3.2GHz。室温下典型功耗电流90mA,最高工作频率大于400MHz。电路芯片面积1.8mm×2.9mm。
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| 关 键 词： | 计数器 触发器 温度 补偿网络 设计 |
Design of an ECL Presetable 4-Bit Binary Decrement Counter |
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| Wang RuoxuSichuan Institute of Solid-State Circuits,Chnogqing,Sichuan. Design of an ECL Presetable 4-Bit Binary Decrement Counter[J]. Microelectronics, 1993, 23(2): 15-21,32 |
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| Authors: | Wang RuoxuSichuan Institute of Solid-State Circuits Chnogqing Sichuan |
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| Affiliation: | Wang RuoxuSichuan Institute of Solid-State Circuits,Chnogqing,Sichuan,630060 |
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| Abstract: | An ECL presetable 4-bit binary decrement counter was top-down designed according to user's specfica-tions. Results from computer modeling show good agreement with design requirements. The circuit was designed in Sum design rule and fabricated with oxide isolated isoplanar S bipolar technology and all ion implantation technique. The minimum emitter line is 3umx10um and thefr for the transistor is 3. 2GHz. A typical maximall operating frequency greater than 400MHz were achieved. The chip area is 1. 8mmx 2. 9mm. |
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| Keywords: | Decrement counter T flip-flop Temperature compensation network ECL circuit |
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