| 基于FPGA实现的高速等效采集系统 |
| |
| 引用本文： | 刘俊斌,吴松林,周卫星.基于FPGA实现的高速等效采集系统[J].电子技术应用,2011(10):84-86. |
| |
| 作者姓名： | 刘俊斌 吴松林 周卫星 |
| |
| 作者单位： | 华南师范大学物理与电信工程学院,广东广州,510006 |
| |
| 摘 要： | 基于FPGA设计一个高速等效采集系统,采样速率高达1 GHz.通过对被测信号的周期进行测量,动态配置锁相环,使采样时钟的周期刚好比被测信号的周期大1ns,从而完成对被测信号的等效采样.系统采用Quartus Ⅱ软件进行系统模块设计,使用NIOS IDE Ⅱ软件完成软件代码的实现.该系统在以Cyclone Ⅲ FPGA芯...
|
| 关 键 词： | 高速等效采样 FPGA 可重配置锁相环 |
A equivalent sampling system based on FPGA |
| |
| Liu Junbin,Wu Songlin,Zhou Weixing.A equivalent sampling system based on FPGA[J].Application of Electronic Technique,2011(10):84-86. |
| |
| Authors: | Liu Junbin Wu Songlin Zhou Weixing |
| |
| Abstract: | It has introduced the equivalent of a high-speed FPGA-based sampling systems,sampling rates up to 1 GHz.To complete the equivalent of the measured signal sampling,by measuring the measured signal cycle,re-configure the Phase Locked loop and the cycle of sampling is bigger than measured signal as much as 1 ns.The Quartus Ⅱ software is used to design system and the NIOS IDE Ⅱ software is used to complete the realization of software code,the whole system is based on DE0 development board with Cyclone Ⅲ FPGA chip. |
| |
| Keywords: | high-speed equivalent sampling FPGA reconfigurable phase locked loop |
| 本文献已被 万方数据 等数据库收录！ |
|
