一种基于FPGA的3DES加密算法实现

为了满足大量连续数据加解密的要求以及提高加密算法安全性的要求,采用有限状态机和流水线等关键技术,设计并实现了基于FPGA的3DES加密算法的加密电路.在Xilinx Virtex4系列的FPGA平台上采用ISE 10.1开发工具实现仿真验证和逻辑综合.结果表明,3DES加密系统的加解密速度可以达到860.660Mb/s,提高了加解密速度,并且有效减少了资源占用率.最终,系统可广泛应用于网络安全产品及其他安全设备中.

3DES implementation based on FPGA

In order to meet the demand of plenty continuous encrypting-deciphering,and meet the demand of enhancing the security of encrypting-deciphering algorithm,the fundamental technologies such as pipeline technology and finite state machine（FSM） are applied,3DES encryption algorithm′s encryption chip′s circuit based on FPGA are designed and realized.On the platform of FPGA of Xilinx Virtex4 series,the ISE 10.1 development kits is used to realize the simulation confirmation and the logic synthesis.The result indicates that the 3DES cryptographic system＇s speed is able to achieve 860.660Mbps,and the encrypting-deciphering speed is greatly enhanced.The design could be used in network security products and other security equipment extensively.