| EPLD可编程器件设计实验开发 |
| |
| 引用本文： | 黄惠英,费铸增. EPLD可编程器件设计实验开发[J]. 北京邮电大学学报, 2000, 23(2): 43-47 |
| |
| 作者姓名： | 黄惠英 费铸增 |
| |
| 作者单位： | 北京邮电大学电子工程系,北京100876 |
| |
| 摘 要： | 应用VLSI技术和CAD技术,根据EPLD可编程技术具有功能集成度高,系统设计加快,设计灵活,可靠性高,费用低的特点,利用美国Altera公司开发的MAX+PLUS软件,研究开发EPLD可编程器件设计专业实验,用于促进学生理论与实际结合及工程实际应用.
|
| 关 键 词： | 超大规模集成电路技术 可擦可编逻辑器件 超高速集成电路硬件描述语言 |
| 收稿时间： | 1999-11-18 |
| 修稿时间： | 1999-11-18 |
Development of EPLD Programmable Device Design Test |
| |
| HUANG Hui-ying,FEI Zhu-zeng. Development of EPLD Programmable Device Design Test[J]. Journal of Beijing University of Posts and Telecommunications, 2000, 23(2): 43-47 |
| |
| Authors: | HUANG Hui-ying FEI Zhu-zeng |
| |
| Affiliation: | Department of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing 1000876,China |
| |
| Abstract: | According to the features of rapid and flexible design, high reliability and low cost of EPLD programmable technology, using VLSI, CAD and MAX+PLUS II developed by Altera company, research and develop EPLD (Erased Programmable Logic Device) design specialty test. This experiment can be used to promote the ability of engineering practice and to combination of practice and theory of students. |
| |
| Keywords: | |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
| 点击此处可从《北京邮电大学学报》浏览原始摘要信息 |
|
点击此处可从《北京邮电大学学报》下载全文 |
|
