Haar函数归一化及在数字电路设计中的应用

数字电路设计中,存在着复杂的分布电容和引线电感,信号通过组件甚至导线,都会产生延迟,在输出端可能会出现不是原来所希望的输出.对于组合逻辑电路来说,虽然这种错误的输出是暂时的,信号稳定后错误会消失,但仍会引起工作的不可靠.为避免这种现象,给出了Haar函数归一化的一种方法以及在变量数<6时用ha系数图判断组合逻辑电路险象的方法,该方法具有简单、直观的特点.

Normalizing Haar Function and Its Application in the Design of Digital Circuits

There are complex distribution capacitance and lead wire inductance in the design of digital circuit, the message will be delayed when passing package and wire so that there will be undesired output in output end. In combination logical circuit, this error output is temporal and will disappear when message tends to be stable, but it will make the work unreliable. To avoid this circumstance, this paper puts forward a method for normalizing Haar function and judging dangerous appearance in combination logic circuit by use of ha coefficient map under the condition of variable number<6. This method has the characteristics of being simple and direct.