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精确时延模型下满足时延约束的缓冲器数目最小化的算法
引用本文:张轶谦,洪先龙,周强,蔡懿慈. 精确时延模型下满足时延约束的缓冲器数目最小化的算法[J]. 半导体学报, 2004, 25(11): 1409-1415
作者姓名:张轶谦  洪先龙  周强  蔡懿慈
作者单位:清华大学计算机科学与技术系 北京100084(张轶谦,洪先龙,周强),清华大学计算机科学与技术系 北京100084(蔡懿慈)
基金项目:国家自然科学基金 , 国家高技术研究发展计划(863计划)
摘    要:提出了在精确时延模型下,满足时延约束的缓冲器数目最小化的算法.给出一个两端线网,该算法可以求出满足时延约束的最小缓冲器数目.运用高阶时延模型计算互连线的时延,运用基于查找表的非线性时延模型计算缓冲器的时延.实验结果证明此算法有效地优化了缓冲器插入数目和线网的时延,在二者之间取得了较好的折中.算法的运行时间也是令人满意的

关 键 词:缓冲器插入   互连优化   布图   VLST

Timing Optimization by Inserting Minimum Buffers with Accurate Delay Models
Zhang Yiqian,Hong Xianlong,Zhou Qiang,Cai Yici. Timing Optimization by Inserting Minimum Buffers with Accurate Delay Models[J]. Chinese Journal of Semiconductors, 2004, 25(11): 1409-1415
Authors:Zhang Yiqian  Hong Xianlong  Zhou Qiang  Cai Yici
Abstract:An algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented.Given a two-terminal net,the algorithm can minimize the total number of buffers inserted to meet the delay constraint.A high order delay model is applied to estimate interconnect delay and a nonlinear delay model based on look-up table is for buffer delay estimation.The experimental results show that the algorithm can efficiently achieve the trade-offs between number of buffers and delay,and avoid needless power and area cost.The running time is satisfactory.
Keywords:buffer insertion  interconnect optimization  layout  VLSI
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