基于Verilog HDL的高效状态机设计

用Verilog HDL(硬件描述语言)进行有限状态机电路设计,由于设计方法不同,综合出来的电路结构、速度、面积和时延特性都会有很大的差别,甚至某些臃肿的电路还会产生难以预料的问题。因此,很有必要深入探讨在用Verilog HDL进行有限状态机设计中,如何简化电路结构、优化电路设计的问题。文中根据有限状态机的设计原理,描述了有限状态机设计的几种设计方法,分析了影响状态机设计时延、速度和电路综合面积问题,提出了一种高效状态机设计方法,并给出了基于Veril-og HDL程序综合得到的电路图,验证了方法的正确性。

Design of High Efficient State Machine Based on Verilog HDL

When designing the finite state machines with Verilog HDL program,there are great differences in the synthesised circuit structure,speed,area and delay due to the different design methods.Furthermore,some redundant circuits may cause unforeseen problems.As a result,it's necessary to discuss how to simplify the circuit structure and optimize the circuit design.Based on the design principle of the finite state machines,several design methods are described.At the same time,the influences on designed delay,speed and synthesis area are analyzed.Furthermore,one design method of high efficient state machines are suggested and it has been validated by the circuit diagrams which are synthesized from the Verilog HDL program.