| 基于FPGA的CRC编解码器实现 |
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| 引用本文： | 孙志雄,谢海霞.基于FPGA的CRC编解码器实现[J].电子器件,2012,35(6):657-660. |
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| 作者姓名： | 孙志雄 谢海霞 |
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| 作者单位： | 琼州学院电子信息工程学院 |
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| 基金项目： | 海南省自然科学基金项目(611133);三亚市院地科技合作项目(2010YD33);三亚市院地科技合作项目(2011YD03);琼州学院校级青年科学基金项目(QYQN201242) |
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| 摘 要： | 循环冗余校验(CRC)是一种广泛应用于通信领域以提高数据传输可靠性的差错控制方法。介绍了CRC码的原理,分析了CRC编码、解码电路设计思路。利用VHDL语言设计CRC(7,3)编解码器并通过QuartusⅡ仿真平台进行仿真验证,最后下载到FPGA芯片实现了CRC(7,3)编解码电路。仿真及实验结果表明采用此方法实现的CRC编解码器具有速度快、可靠性高及易于大规模集成的优点。
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| 关 键 词： | CRC 编码器 解码器 FPGA VHDL |
Implementation of CRC Encoder and Decoder based on FPGA |
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| SUN Zhixiong,XIE Haixia.Implementation of CRC Encoder and Decoder based on FPGA[J].Journal of Electron Devices,2012,35(6):657-660. |
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| Authors: | SUN Zhixiong XIE Haixia |
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| Affiliation: | (College of Electronics and Information Engineering,Qiongzhou University,Sanya Hainan 572022,China) |
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| Abstract: | The Cyclic Redundancy Check (CRC) is a widely used error control method in communicating fields to improve the reliability for data transmission. This paper introduces the principle of CRC code and the ideas on designing CRC encoder and decoder. After designing and simulating the CRC(7,3) with VHDL language on Quartus II ,the programming data files are downloaded to implement the design of CRC(7,3) encoder and decoder with FPGA chip at the last. The simulation and experiment results show that using this method to achieve the CRC encoder and decoder with fast speed, high reliability and easy large scale integration advantages. |
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