基于FPGA的Montgomery模乘器的高效实现*

为了提高椭圆曲线密码处理器的模乘速度，本文提出了一种更有效且更适合硬件实现的Montgomery算法。改进的算法分析了基于CSA加法器的Montgomery模乘算法，提出了多步CSA加法器的Montgomery算法，该算法能够在一个时钟内做多次CSA迭代运算，可以有效地降低时钟个数，进而提高模乘速度。通过Modelsim仿真工具仿真，正确完成一次256bits Montgomery模乘运算只需要16个时钟周期。在Altera EP3SL200F1517C2 FPGA中的运行结果表明：71.5MHz的时钟频率下，完成一次256位的模乘运算仅需要0.22微秒。

Efficient Implementation of Montgomery Modular Multiplier on FPGA

To improve the speed of modular multiplication operation on ECC processor, this paper shows an improved Montgomery algorithm that is more efficient and suitable for hardware implementation. First, the improved algorithm analyzes the Montgomery modular multiplication algorithm based on CSA adder, then presents the multi-step CSA adder Montgomery algorithm. The idea of multi-step expresses that improved algorithm can do repeatedly CSA iterations in one clock. Therefore, the improved modular multiplication can increase the speed of modular multiplication by reducing the number of clocks. Simulation with Modelsim indicates that an accurate completion of modular multiplication requires only 16 clock circles. And the simulation on Altera EP3SL200F1517C2 FPGA shows that a modular multiplication of 256 bits only takes 0.22us under 71.5MHz clock frequency.