Impact of High-κ Offset Spacer in 65-nm Node SOI Devices

In this letter, 65-nm node silicon-on-insulator devices with high-kappa offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-kappa offset spacer dielectric can effectively increase the on-state driving current I_ON and reduce the off leakage current I_OFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the I_ON/I_OFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-kappa offset spacer dielectric