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AVS编码器帧内预测模块
引用本文:刘华北,王树昆,朱传德.AVS编码器帧内预测模块[J].计算机系统应用,2015,24(1):191-194.
作者姓名:刘华北  王树昆  朱传德
作者单位:山东建筑大学信息与电气工程学院,济南,250101
摘    要:通过对AVS(Audio and Video Standard,音视频编码标准)标准中帧内预测算法的分析,提出了一种新的适用于AVS编码器帧内预测模块的优化设计方案.设计中使用两维滤波单元,简化了参考数据选择机制;使用设计的基本预测单元PE(Primary Element)构造运算单元阵列对当前块进行并行处理,提高了预测速度;设计了脉动阵列用于实现复杂色度Plane模式的预测.基于Verilog HDL语言在FPGA上实现该设计并在ModelSim上进行仿真,结果表明,本设计提高了编码效率以及降低硬件资源的消耗,并满足实时编码高清视频的要求.

关 键 词:AVS标准  视频编码  帧内预测  并行处理
收稿时间:2014/4/21 0:00:00
修稿时间:5/9/2014 12:00:00 AM

Intra Prediction in AVS Video Encoding
LIU Hua-Bei,WANG Shu-Kun and ZHU Chuan-De.Intra Prediction in AVS Video Encoding[J].Computer Systems& Applications,2015,24(1):191-194.
Authors:LIU Hua-Bei  WANG Shu-Kun and ZHU Chuan-De
Affiliation:School of Information and Electical Engineering, Shandong Jianzhu University, Jinan 250101, China;School of Information and Electical Engineering, Shandong Jianzhu University, Jinan 250101, China;School of Information and Electical Engineering, Shandong Jianzhu University, Jinan 250101, China
Abstract:Through the analysis of the Audio and Video Standard intra prediction algorithm, a new optimization design method is put forward to the AVS encoder intra prediction module. Two dimensional filtering units were used in the design simplifying the reference data selection mechanism. Using the prediction unit array constructed by the basic unit PE improves the prediction speed. Design of systolic arrays is used to predict complex color Plane mode. The design based on the Verilog Hardware Design Language(HDL)is realized on FPGA and simulated in ModelSim. The results show that this design improves the coding efficiency and reduces the consumption of hardware resources and meet the requirements of real-time encoding of high-definition video.
Keywords:AVS standard  video coding  intra prediction  parallel processing
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