基于码密度法的时间数字转换器非线性校正方法研究

运用码密度的方法解决了FPGA内部专用进位链延迟单元的非线性问题,提高了FPGA中时间数字转换器(TDC)的测时精度.通过研究发现FPGA中进位链非线性是造成TDC测试精度降低的主要原因,针对这一问题,采用了统计学的码密度法进行了非线性校正,并确定了样本的数量以及校准值的选取.在EP2C5T144C8芯片内构建了TDC和校准模块,通过输入近似的大量随机跳变信号,得到延迟单元的准确延迟时间和非线性测试结果.实验结果表明,运用码密度法可以准确地反映出延迟时间在TDC中的分布情况.

Research on Non-Linear Calibration for Time to Digital Converter Based on Code Density Distribution

In order to improve the measurement accuracy of time to digital converter (TDC) that consists of carry chain inside FPGA,the code density distribution is used to calibrate the nonlinearity of the carry chain.The research finds that decrease of accuracy is mainly caused by the nonlinearity of carry chain.To calibrate the carry chain,a statistical method based on the code density distribution of the carry chain is adopted.The determinations of the sample quantity and correction value are elaborated.Then the TDC and calibration module are built in FPGA,a large number of approximate random hits are imported into the TDC to get the code density distribution.Finally the accurate delay time of each unit and the final nonlinear test result are obtained.Experimental results show that the method of code density distribution can accurately reflect the delay distribution of the TDC.