A BiCMOS PLL-based data separator circuit with high stability andaccuracy |
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Authors: | Miyazawa S. Horita R. Hase K. Kato K. Kojima S. |
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Affiliation: | Hitachi Ltd., Yokohama; |
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Abstract: | A data separator that can work in Winchester disk drives at a read/write speed of up to 30 Mb/s is described. To realize high stability and accuracy in reproducing data in high-speed transfers, a digital synchronization field detector and an analog dual-mode phase-locked loop (PLL) that has a phase detector which has constant gain in the data field, independent of pattern, are used. The dual-mode analog PLL has a wide decode margin, locks up quickly, and operates stably without being affected by the frequency deviation of data. The digital sync field detector is adjustment-free and detects sync fields very accurately. The IC incorporates a RLL 2-7 code encoder/decoder and a write compensator. Use of the 2-μm BiCMOS process keeps the total power consumption as low as 400 mW even at the high transfer rate of 30 Mb/s |
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