A 27-mW 3.6-gb/s I/O transceiver |
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| Authors: | Wong K.-L.J. Hatamkhani H. Mansuri M. Yang C.-K.K. |
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| Affiliation: | Univ. of California, Los Angeles, CA, USA; |
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| Abstract: | This paper describes a 3.6-Gb/s 27-mW transceiver for chip-to-chip applications. A voltage-mode transmitter is proposed that equalizes the channel while maintaining impedance matching. A comparator is proposed that achieves sampling bandwidth control and offset compensation. A novel timing recovery circuit controls the phase by mismatching the current in the charge pump. The architecture maintains high signal integrity while each port consumes only 7.5 mW/Gb/s. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology. |
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