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基于FPGA的IEEE802.11协议帧生成器的设计
引用本文:方翌炜,方华京.基于FPGA的IEEE802.11协议帧生成器的设计[J].微计算机信息,2007,23(20):161-164.
作者姓名:方翌炜  方华京
作者单位:1. 430074,武汉,华中科技大学电子信息工程系
2. 430074,武汉,华中科技大学控制科学与工程系
摘    要:IEEE 802.11, the most popular standard, defines the protocols which covers all of Ethernet based wireless communication. This paper presented an implementation of IEEE 802.11 Frame Generator, which used FPGA as a hardware platform. This generator constructs the 802.11 frame and supplied it to DSSS as signal to be sent. There are 3 modules in this design. The 1st is the global control module, the 2nd module is CRC- 32 check and the 3rd is used to produce frame serial number. The characteristic of this de- sign is that the signal process and the transmission are made at the same time, i.e. real time processing. That is important to the wireless network device, which has narrower bandwidth and lower process energy. The Verilog HDL codes, block diagram of the whole system, and the simulation results were described in this paper.

关 键 词:802.11协议  帧生成
文章编号:1008-0570(2007)07-2-0161-02
修稿时间:2007-04-23

Design and implementation of IEEE 802.11 Frame Generator based on FPGA
FANG YIWEI,FANG HUAJING.Design and implementation of IEEE 802.11 Frame Generator based on FPGA[J].Control & Automation,2007,23(20):161-164.
Authors:FANG YIWEI  FANG HUAJING
Affiliation:FANG YIWEI FANG HUAJING
Abstract:IEEE 802.11, the most popular standard, defines the protocols which covers all of Ethernet based wireless communication. This paper presented an implementation of IEEE 802.11 Frame Generator, which used FPGA as a hardware platform. This generator constructs the 802.11 frame and supplied it to DSSS as signal to be sent. There are 3 modules in this design. The 1st is the global control module, the 2nd module is CRC-32 check and the 3rd is used to produce frame serial number. The characteristic of this de-sign is that the signal process and the transmission are made at the same time, i.e. real time processing. That is important to the wireless network device, which has narrower bandwidth and lower process energy. The Verilog HDL codes, block diagram of the whole system, and the simulation results were described in this paper.
Keywords:FPGA  FPGA  802  11  protocol  frame generator
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