A portable digital DLL for high-speed CMOS interface circuits |
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| Authors: | Garlepp B.W. Donnelly K.S. Jun Kim Chau P.S. Zerbe J.L. Huang C. Tran C.V. Portmann C.L. Stark D. Yiu-Fai Chan Lee T.H. Horowitz M.A. |
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| Affiliation: | Rambus Inc., Mountain View, CA; |
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| Abstract: | A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-μm standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-speed interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm2 |
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