A phase locked motor speed control system with sample-and-holdphase detector

A phase-locked speed-control with a sample-and-hold phase detector, which replaces the common phase detector and lowpass filter thus reducing the system's response time, is investigated. The phase detector's nonlinear behavior when operating inside the loop is discussed, together with the related lower speed limit. The system's operating region is determined by calculating the phase-locked loop (PLL) hold-in range and control system stability limits. Analytical expressions, along with related diagrams, illustrate the role of each of the system, parameters. Minimum system speed is also considered and its improvement through the use of various compensating networks is examined