A high-speed programmable CMOS interface system combining D/Aconversion and FIR filtering |
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Authors: | Henriques B.G. Franca J.E. |
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Affiliation: | Dept. of Electr. & Comput. Eng., Inst. Superior Tecnico, Lisbon; |
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Abstract: | This paper describes the design, integrated circuit realization, and experimental characterization of a high-speed programmable interface system combining the functions of digital-to-analog (D/A) conversion and FIR filtering. The system comprises four high-speed digital delay lines, with programmable delay length, together with four high-speed steering-current D/A converters with independent digitally-programmable gains. A demonstration prototype chip has been fabricated in a 1.2-μm digital CMOS technology. At 54 MHz conversion rate and digital delay lines clocked at 18 MHz, it consumes 115 mW for a full-scale output current of 13.3 mA at 5 V supply |
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