Automated analysis structures for BiCMOS process simulation, development, and verification

This paper presents a system of BiCMOS process step simulation, development, and verification using automatically generated physical test structures. During process development, detailed unit process step deliverables are compiled in a document called the process technology table (PTT). These targets are initially set by equipment capabilities, product needs, and process simulations, but every PTT entry must be ultimately verified on silicon. Therefore, the process development engineers require a method of specifying, simulating, and analyzing a large variety of process test structures. A computer-aided design system to do this has been developed. The particulars of its use during the integration of a 0.35-/spl mu/m BiCMOS process flow are presented. Details about a novel cross-sectional structure labeling and identification scheme are also presented.